Cabinet approves the Tata Electronics-PSMC fab: Rs 91,000 crore, up to 50,000 wafers a month

The planned process generations are mature ones rather than cutting-edge: 90, 110, 55, 40 and 28 nanometres, for power management chips, display drivers, microcontrollers and computing logic. The fab is expected to open mostly at 90 nm, the most mature of those. It is not expected to open at 28 nm, but that is the number most often quoted about it, and the difference matters because a mature process generation is a different business from a leading-edge one. Ground-breaking followed in March 2024. As of mid-2026 civil work is reported past halfway, with cleanroom fit-out and equipment calibration under way. A December 2026 date for first silicon, meaning the first wafers run through the line, is widely repeated and is a target rather than a supported fact. No source we hold confirms it. What is reported is that commercial production is guiding to mid-2028.

More than 20,000 direct and indirect jobs are projected. No source confirms a chip produced yet, and this ledger will record that day when a primary source does.